The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei 11-186713 filed Jun. 30, 1999 in Japan to which the subject application claims priority under the Paris Convention and which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to an exposure process in manufacturing semiconductor devices and the display elements of, for example, liquid-crystal display panels, and particularly, to an exposure method, a reticle, and a method of manufacturing semiconductor devices, capable of reducing arrangement errors.
2. Description of the Related Art
Manufacturing semiconductor devices and the display elements of, for example, liquid-crystal display panels involves an exposure process. The exposure process employs a reticle, or a mask having device patterns and repeatedly projects the patterns on a wafer through step-and-repeat operations with the use of an exposure system. A layout of the patterns on a wafer is designed to maximize the number of devices or chips to be produced from the wafer. According to the layout, a layout of shots on the wafer is determined. A shot is a unit of exposure carried out by an exposure system with respect to a wafer, and a shot area on the wafer is determined by a shot area on a reticle of the exposure system. To improve productivity, the shot area must cover a plurality of device or chip patterns so that a plurality of devices are simultaneously exposed on a wafer.
The number of device patterns contained in a shot area is determined by the size of each device pattern and the maximum angle of view of an exposure system. An exposure system having a large shot area is capable of simultaneously exposing a larger number of device patterns, to improve productivity.
Prior arts usually employ the same shot layout from the first to last exposure layers when forming device patterns on a wafer. Recent price and system situations, however, impose a requirement of employing exposure systems of different shot areas in combination to expose a wafer when manufacturing semiconductor devices. To meet the requirement, a prior art equalizes the shot areas of exposure systems by restricting the using area of reticle of each exposure system. Namely, the prior art reduces the large shot area of a high-performance exposure system to the small shot area of a low-performance exposure system. As a result, the prior art prevents, the high-performance exposure system from fully operating, unnecessarily increases the number of shots with the restricted shot area, and deteriorates throughputs.
The present invention enables exposure systems of different shot areas to operate as they are when manufacturing semiconductor devices.
FIG. 1A shows a shot area 11 of an exposure system 21 and FIG. 1B shows a shot area 12 of an exposure system 22. The shot area 11 of FIG. 1A has a size of 25 mm by 33 mm and covers three device patterns 6 each of 22 mm by 11 mm. The device patterns 6 are formed on a reticle. The shot area 12 of FIG. 1B has a size of 22 mm by 22 mm and covers two device patterns 8 each of the same size as the device pattern 6. The device patterns 8 are formed on a reticle. When manufacturing semiconductor devices, a first exposure process employs the exposure system 21 to form the device patterns 6 on a wafer, and a second exposure process employs the exposure system 22 to form the device patterns 8 on the wafer.
FIG. 2 shows the device patterns 6 and 8 formed on a wafer with the use of the shot areas 11 and 12 of the exposure systems 21 and 22 as they are. Positional relationships among the device patterns of FIG. 2 are exaggerated. The first exposure process forms pattern groups 13 and 14 each consisting of three device patterns 6. A bottom side of the pattern group 13 disagrees with a top side of the pattern group 14. This disagreement is an arrangement error.
The second exposure process superposes the device patterns 8 on the device patterns 6 on the wafer. Two device patterns 8 of a pattern group 15 are formed on the upper two device patterns 6 of the pattern group 13. To align the pattern groups 13 and 15 with each other, the first exposure process forms first alignment marks. The second exposure process employs second alignment marks, detects the first alignment marks, and adjusts the second alignment marks to the detected first alignment marks. This alignment work may correctly be carried out by employing an enhanced global alignment (EGA) technique that reads the positions of the first alignment marks, calculates arrangement errors according to the read marks, and corrects the second exposure process according to the calculated arrangement errors. Two device patterns 8 of a pattern group 16 are formed on the lowermost device pattern 6 of the pattern group 13 and the uppermost device pattern 6 of the pattern group 14. Two device patterns 8 of a pattern group 17 are formed on the lower two device patterns 6 of the pattern group 14. If the upper device pattern 8 of the pattern group 16 is aligned with the lowermost device pattern 6 of the pattern group 13, the lower device pattern 8 of the pattern group 16 does not align with the uppermost device pattern 6 of the pattern group 14. This is a superposition error. If the first exposure process causes an arrangement error in the device patterns 6, the second exposure process causes a superposition error. A process that allows a large superposition error, such as a process of forming openings on a polyimide film may accept two exposure systems of different shot areas to be used as they are. However, a process that scarcely allows superposition errors never accepts two exposure systems of different shot areas to be used as they are.
To reduce superposition errors between first and second exposure processes, no prior art has tried to reduce arrangement errors.
An object of the present invention is to provide an exposure method capable of reducing arrangement errors so that exposure systems may effectively use their shot areas even for a process that scarcely allows superposition errors.
Another object of the present invention is to provide a reticle applicable to the exposure method capable of reducing arrangement errors so that exposure systems may effectively use their shot areas even for a process that scarcely allows superposition errors.
Still another object of the present invention is to provide a method of manufacturing semiconductor devices, capable of reducing arrangement errors so that exposure systems may effectively use their shot areas even for a process that scarcely allows superposition errors.
In order to accomplish the objects, a first aspect of the present invention provides an exposure method including the steps of forming, in a shot area on a reticle, marks to measure arrangement errors that may occur between adjacent device patterns, transferring the marks from the reticle onto a wafer through exposure and development processes using an exposure system, measuring arrangement errors according to the marks on the wafer, calculating four error components from the measured arrangement errors, and correcting the exposure system according to the calculated error components. The first aspect reduces arrangement errors.
The first aspect may form at least one mark on each side of the shot area of the reticle, to secure the error correcting effect. The first aspect can measure arrangement errors between adjacent pattern groups along each side of the pattern groups, the pattern groups being formed on the wafer and each corresponding to the shot area of the reticle. This improves the correct positioning of pattern groups over the entire surface of the wafer.
According to the first aspect, the marks may be box-in-box marks or bars-in-bars marks serving as outer and inner marks. The box-in-box marks consist of large and small squares so that the small square may fit in the large square, a positional relationship between the large and small squares being used to correctly position device patterns on a wafer. The bars-in-bars marks consist of a plurality of bars instead of the squares. In the box-in-box marks, the large square is an outer mark and the small square is an inner mark. These marks are used to measure positional and arrangement errors related to device patterns formed on a wafer.
A second aspect of the present invention provides a reticle. The reticle has a shot area of rectangular or square shape, at least one device pattern formed in the shot area, a first mark having a first aligning point and formed inside the shot area and outside the device pattern in the vicinity of a first side of the shot area, and a second mark having a second aligning point and formed inside the shot area and outside the device pattern in the vicinity of a second side of the shot area opposite to the first side. A first straight line that connects the first and second aligning points is perpendicular to the first side. The first and second marks are distinguishable from each other. If the marks are box-in-box marks, the aligning point of each box mark is the center thereof. If there is no arrangement error, the aligning points of corresponding box marks agree with each other. To make the first and second marks distinguishable from each other even if they are superposed one upon another, the first and second marks have different shapes or sizes. The reticle of the second aspect is applicable to the exposure method that is capable of reducing arrangement errors.
A third aspect of the present invention provides a method of manufacturing semiconductor devices, including the steps of carrying out an exposure process on a wafer according to the exposure method of the first aspect, and carrying out an exposure process on the wafer to superpose patterns on the patterns that have been formed by the first exposure process. The third aspect manufactures semiconductor devices having minimized arrangement errors.
The third aspect is effective when the size of a shot area for the first exposure process differs from the size of a shot area for the second exposure process. The third aspect is capable of manufacturing semiconductor devices by using exposure systems of different shot areas without restricting the shot areas.
The first exposure process of the third aspect may be an exposure process carried out on the wafer for the first time. In this case, the third aspect reduces superposition errors caused by arrangement errors through all exposure processes.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.